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TestGenie - Getting started with Low-cost Boundary Scan |
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TestGenie is a package consisting of ScanExpress executable software components and a JTAG controller from Corelis, which allows users to start their boundary scan experience at very reasonable costs at with almost no effort to introduce this technology into their production process.
Included in the TestGenie package is the test plan generation for your product based on your netlist, the bill of material and BSDL files from the silicon vendors. With the testplan generation being part of the offer, it will only take a few days before you can get your test up and running. There is no need to get involved in creating your own test plan which of course can be the next step if you are satisfied with what you received. We are here to help you get started with TestGenie and the other ScanExpress tools Corelis has to offer.
Please contact us for details and a quotation if you consider using boundary scan technology. You will be surprised how easy and how inexpensive it is to begin making use of this technology. |
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Last Updated on Friday, 16 September 2011 09:37 |
Boundary-scan, as defined by the IEEE Std. 1149.1 standard, is an integrated method for testing interconnects on printed circuit boards that is implemented at the IC level. The inability to test highly complex and dense printed circuit boards using traditional in-circuit testers and bed of nail fixtures was already evident in the mid eighties. Due to physical space constraints and loss of physical access to fine pitch components and BGA devices, fixturing cost increased dramatically while fixture reliability decreased at the same time.
In the 1980s, the Joint Test Action Group (JTAG) developed a specification for boundary-scan testing that was standardized in 1990 as the IEEE Std. 1149.1-1990. In 1993 a new revision to the IEEE Std. 1149.1 standard was introduced (titled 1149.1a) and it contained many clarifications, corrections, and enhancements. In 1994, a supplement that contains a description of the boundary-scan Description Language (BSDL) was added to the standard. Since that time, this standard has been adopted by major electronics companies all over the world. Applications are found in high volume, high-end consumer products, telecommunication products, defense systems, computers, peripherals, and avionics. Now, due to its economic advantages, smaller companies that cannot afford expensive in-circuit testers are using boundary-scan.
A large number of links to BDSL libraries is available at the Corelis' website.
For more detailed information on Boundary Scan, please refer to the Boundary Scan Tutorial located on the Corelis website.
If you wish to discuss your test and programming requirements, please, feel free to contact us.
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Last Updated on Saturday, 21 January 2012 17:14 |
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Corelis Boundary Scan Systems |
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Corelis offers a complete product line of JTAG (boundary-scan) tools called ScanExpress for interconnect testing and JTAG in-system programming of flash memories and CPLDs. ScanExpress software has an intuitive graphical user interface for the generation and execuftion of Boundary Scan test vectors under Windows 2000/XP/Vista. Furthermore, DLLs fof these functionsor integration National Instruments' LabView, LabWindows/CVI, TestStand, Geotest ATEasy, Agilent's VEE, Visual Basic and C++ are available.
A wide selection of JTAG (boundary-scan) hardware controllers is available from Corelis, including PCI, PCI Express, USB 2.0, Ethernet/LAN, PXI/cPCI and VXI, with price and performance to meet your specific requirements. For performance critical JTAG applications, Corelis offers boundary-scan controllers that operate at up to 100MHz sustained TCK frequency, enabling fast board JTAG interconnect testing and JTAG programming of flash memories at their maximum theoretical speed.
The high performance CAS-1000 I2C/E I2C bus analyzer and exerciser is an enhanced model targeted towards IC verification and parametric testing. The CAS-1000-I2C/E hardware provides more advanced features such as master and slave emulation, bus specification validation, bus parameter measurement, glitch injection, clock stretching, and adjustable timing skew.
In conjunction with Corelis ScanExpress software, the CAS-1000 controller can be used for Boundary Scan testing of complete boards as well as for (interconnect test, etc.) as well as for in-system-programming of Flash memory and CPLDs.
Read more on the how to debug a dead board at Corelis' website.
More information on Corelis Boundary Scan products is available on request.
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Last Updated on Wednesday, 19 May 2010 10:14 |
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Note: If in doubt which products or product combination suits your testing and programming needs, please, feel free to contact us.
ScanExpress Programmer
ScanExpress Programmer offers several programming methods. Utilizing a high-performance Corelis controller with built-in support for JTAG, I2C, and SPI, and user friendly Windows-based software, ScanExpress Programmer can program components utilizing any of four individually licensed modules: SPI Programmer I2C Programmer Target Assisted Flash Programmer (TAFP) JTAG Programmer. more...
ScanExpress Debugger
The ScanExpress Debugger is an excellent tool for engineers doing debug during prototype design verification and testing. It is very useful for finding shorts and opens on and between BGA devices and other fine-pitch components. The ScanExpress Debugger allows interactive control and observation of all the boundary-scan controllable inputs and outputs on a Unit Under Test (UUT). It can also apply data to inputs of clusters and read their responses if the cluster I/Os are accessible via boundary-scan components.
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ScanExpress Runner
The ScanPlus system includes the ability to execute boundary-scan tests and perform In-System Programming in a pre-planned specific order called a test plan. Test vectors, in the form of Compact Vector Format (CVF) files which have been generated using ScanExpress TPG, can be automatically executed and the results displayed and logged to a file. Other formats such as SVF, JAM, STAPL, and J-Drive are also supported. Different test plans may be constructed for different UUT's. Tests within a test plan may be reordered, enabled or disabled. An unlimited number of different tests can be combined into a test plan. The software used to run these tests is ScanPlus Runner.
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Target Assisted Flash Programmer (TAFP)
The Target Assisted Flash Programmer takes advantage of the embedded CPU on the target board to shorten the Flash memory programming time and simplify the operation of Flash programming. With the Target Assisted Flash Programmer, the user can perform many Flash programming functions such as erase, blank check, program, verify, obtain device ID, etc. All of these functions can be performed while the device is installed in-circuit. The Target Assisted Flash Programmer has the ability to test the JTAG connection, test the RAM, check the Flash device ID, erase the Flash device, verify the erasure, download Flash data to RAM, program the Flash device, and verify the Flash data in one step.
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ScanExpress JET
JTAG Emulation Test (JET) makes automatic test generation of structural and functional testing a reality. This test methodology extends coverage beyond popular boundary-scan techniques to virtually every signal accessible by an on-board processor (CPU). It drastically improves test coverage and diagnostic information. JET testing is dependent on the UUT having a JTAG-enabled CPU on-board. The JET method harnesses the power of the target embedded CPU to assist in the code download, device programming and testing operations, at full processing speed.
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Last Updated on Wednesday, 19 May 2010 10:16 |
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Boundary Scan
The Corelis